Multiprocessor systems are becoming increasingly prevalent in even low-cost devices. Multiprocessor environments usually have at least one resource, such as a memory, that is shared by the processors, where access to the shared resource is typically controlled through locks. A lock or semaphore is obtained by a processor to gain exclusive access over a particular location in the shared memory. Through the lock, the processor can without ambiguity, see if the lock is owned and if not, indicate that it owns the lock.
An atomic instruction is implemented using a lock to allow one processor to determine if it was successful in acquiring the lock without interference from another competing processor. Examples of atomic instructions are TAS (Test and Set) and SWAP (SWAP memory contents with register contents).
Another method for achieving the atomic behavior is the method used by MIPS processors that perform a LL (Load Linked), which reads the memory location. The processor then performs an SC (Store Conditional) to write the locked value to the location. The “link” between the two instructions is the address of the memory accessed. The MIPS snoops the bus and the SC instruction fails if the location is accessed between the LL/SC pair.
The SWAP and TAS instructions are well-known element of a processor instruction set, which may be used in an environment where multiple microprocessors and resources are interconnected through a high-speed bus, such as the AHB bus by ARM of the United Kingdom. Any device capable of initiating read and write request over the AHB bus is referred to as a master device, and devices that respond to the requests are referred to as slave devices. The AHB bus supports a locking feature for the master devices. When an AHB master is granted a request for a locked operation, all other masters are prevented from accessing the bus until the locking master releases it.
The ARM SWAP instruction, which is executed by the master devices, is implemented using the AHB bus locking feature lock. The SWAP instruction includes three register names as parameters. The syntax is as follows:SWAP Rd, Rm, [Rn]Rd is a destination register that is loaded with the contents of memory; Rm contains a value to be written to memory; and Rn contains an address of the target memory location. In operation, the SWAP instruction performs a read of the memory location pointed to by Rn and saves the result in Rd. Next, a write operation is performed that stores the contents of Rm in the memory location pointed to by Rn.
Atomic instructions are an effective way to share resources in a multiprocessor environment. However, multiprocessor systems that mix different types of microprocessors and digital signal processors (DSPs) are now common. The problem is that not all types of processors and DSPs support an atomic operation.
One attempted solution has been to implement a primitive lock through software only (Peterson's Algorithm). The software only approach suffers several disadvantages, however. One disadvantage is that the approach is slow because each processor must cycle through a variable that enables the processor to proceed to a state in which it is allocated the lock. Another disadvantage is that the algorithm is a polled process where each processor continually issues commands over the bus, which induces unnecessary bus traffic. For these reasons, the algorithm becomes cumbersome as the number of competing processes grows and may degrade overall system performance.
Accordingly, what is needed is a method and system for enabling processors that do not support atomic operations to access shared recourses over a bus that supports a locking feature. The present invention addresses such a need.